1. Field
Embodiments relate to the field of directed self assembly. In particular, embodiments relate to aligning or positioning structures formed through directed self assembly.
2. Background Information
Integrated circuits generally include interconnect structures to electrically couple circuitry formed in a semiconductor substrate (e.g., transistors and other circuit elements) with an external signaling medium (e.g., a package, pins, printed circuit board, etc.). Often multi-layer interconnect structures are employed that include multiple levels of generally coplanar metal or other interconnect lines disposed within a dielectric or insulating layer. Vias are generally used to provide select electrical couplings between interconnect lines on different levels by providing electrically conductive paths through the dielectric or insulating materials between the interconnect lines on the different levels.
The metal lines and vias are typically formed by a process that uses lithographic patterning to define their locations and dimensions. In the case of copper interconnect lines commonly found in many modern day processors, a dual damascene type of process is generally employed. Representatively, in one such process, a photoresist layer may be spin coated over a dielectric layer over a substrate, often with thin hard mask layer in between to facilitate etch transfer. Openings for the vias may initially be patterned in the photoresist layer by exposing the photoresist layer to patterned actinic radiation through one or more patterned masks and developing the photoresist layer to form the openings for the vias. The lithographically defined openings for the vias may then be used as an etch mask to etch openings for the vias in the underlying dielectric layer. Subsequently, openings for the metal lines may similarly be formed lithographically in the photoresist layer. The lithographically defined openings for the metal lines may be used as an etch mask to etch trenches or line openings for the metal lines in the underlying dielectric layer. Metal (e.g., one or more barrier layers, bulk copper, etc.) may be introduced into the openings for the vias and the metal lines that have been formed in the dielectric layer. Chemical mechanical polishing (CMP) is commonly used to remove excess metal residing outside of the metal lines. Such a process may generally be repeated to form the additional overlying levels of vias and interconnect lines. Generally, lithography is used to position and align the vias and interconnect lines of an upper/overlying level relative to those on the adjacent lower/underlying level.
There has been a general past and present trend toward ever decreasing sizes and spacing of interconnect structures for at least certain types of integrated circuits (e.g., processors, chipset components, graphics chips, etc.). It is likely that in the future the sizes and spacing of interconnect structures will continue to progressively decrease. One measure of the size of the interconnect structures is their critical dimensions (e.g., the line widths or the widths of the via openings). One measure of the spacing of the interconnects is the pitch (e.g., the line pitch and/or the via pitch). The pitch may represent the center-to-center distance between the closest adjacent interconnect structures (e.g., adjacent lines or adjacent vias).
When patterning extremely small interconnect structures and/or interconnect structures at extremely small pitches by such lithographic processes, several challenges tend to present themselves, especially when the pitches are around 50 nanometers (nm) or less and/or when the critical dimensions of the lines and/or vias are around 20 nm or less. One potential challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances. As pitches (e.g., via pitches) scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.
Another potential challenge is that the critical dimensions of the openings (e.g., the via openings) generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the openings. However, the shrink amount tends to be limited by the minimum pitch, as well as by the ability of the shrink process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU).
Yet another potential challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions decrease in order to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions are decreasing.